Sutherland HDL Inc. To Present At DAC Workshop On SystemVerilog

PORTLAND, OR - MAY 21, 2003--SystemVerilog expert Stuart Sutherland of Sutherland HDL, Inc. has been selected to present a tutorial on compatibility between the IEEE Verilog standard and the proposed Accellera SystemVerilog 3.1 standard at the Accellera SystemVerilog workshop to be held Monday, June 2nd, 2003. This workshop is co-located with the Design Automation Conference (DAC) in Anaheim, California. The tutorial will be presented in the 3:45 PM session of the workshop. This session also includes a discussion of which EDA vendors have announced products supporting SystemVerilog. Details on the Accellera SystemVerilog workshop can be found at www.accellera.org/SystemVerilogWorkshop.html.

Is SystemVerilog in Your Future?

To help engineers prepare for DAC, Sutherland HDL is hosting a special half-day seminar giving a complete overview of the powerful features in SystemVerilog. This seminar will be held in San Jose, California on May 27th, one week before DAC. Engineers and engineering managers who need to know what SystemVerilog has to offer, and what questions to ask their EDA vendors at DAC, will benefit from this seminar. EDA application engineers and technical sales personnel can learn the features of SystemVerilog and how to position their company's products with respect to SystemVerilog. See www.sutherland-hdl.com/seminar.htm for details on this valuable seminar. Seating is limited.

"SystemVerilog is the exciting new set of extensions to the Verilog language that has been developed by the Accellera EDA standards organization", explains Stuart Sutherland, founder and president of Sutherland HDL. "Enhancements such as structures, safe-pointers, and interfaces make it possible to model multi-million gate designs using substantially fewer lines of code. Extensions such as object-oriented classes, mailboxes, semaphores, constrained random number generation and PSL (Sugar) based assertions make it possible to verify these multi-million gate designs using the same language in which the design is modeled."

About Mr. Sutherland and Sutherland HDL. Stuart Sutherland is a member of the IEEE 1364 Verilog standards group as well as the Accellera SystemVerilog standards committee. His in-depth knowledge of both standards provides a comprehensive and accurate view of what SystemVerilog has to offer, and how well these extensions are integrated with the IEEE Verilog standard. As an independent design and training consultant, Mr. Sutherland candidly discusses the features and compatibility of SystemVerilog from an engineer's perspective.

Sutherland HDL, Inc., located in Portland, Oregon, specializes in providing training on SystemVerilog, Verilog HDL, Verilog PLI and VHDL. Company information is available at www.sutherland-hdl.com.

For more information, contact:
Sutherland HDL, Inc.
Stuart Sutherland
503-692-0898
stuart@sutherland-hdl.com